1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor device in which capacitance at an input path of an external signal is decreased.
2. Description of the Background Art
A semiconductor device including an electronic circuitry formed of a number of elements includes bonding pads for exchange of signals between the electronic circuitry and the outside. FIG. 10 shows an example of a bonding pad arrangement in the semiconductor device. Referring to FIG. 10, the semiconductor device includes a semiconductor substrate 100 on the surface of which an electronic circuit 110 and bonding pads 120 are formed. Electronic circuit 110 is provided at the central portion of the semiconductor substrate 100, and bonding pads 120 are provided near the outer side of the semiconductor substrate 100. Each of the bonding pads 120 is connected to electronic circuit 110 by means of interconnection layer 130 formed on the surface of the semiconductor substrate 100. Semiconductor substrate 100 is adhered on a lead frame 220 having external pins 210 allowing exchange of signals with the outside. One external pin 210 is provided for each bonding pad 120. Each of the bonding pad 120 is formed by deposited metal, and is connected to the corresponding external pin 210 by means of a thin metal wire 300.
In this manner, in a semiconductor device, bonding pads are interposed between external pins and an internal circuitry, providing electrical contact therebetween. Since the external pin and the bonding pad are subjected to wire bonding and the length of the wire which can be taken out at one time is limited, the distance between the bonding pad and the external pin should be as short as possible. Therefore, the bonding pads are provided near the outer side of the semiconductor substrate.
A DRAM (Dynamic Random Access Memory) is one of such semiconductor devices requiring such bonding pads. FIG. 11 is a schematic block diagram showing functionally the whole structure of the DRAM. Referring to FIG. 11, a DRAM chip 1 includes a memory cell array MCA including memory cells (not shown) arranged in a matrix of a plurality of rows and a plurality of columns; an address buffer AB, a row decoder RD and a column decoder CD for selecting a memory cell to which or from which data is to be written or read out of the memory cells in memory cell array MCA; a data input circuit DI for taking from the outside a data signal to be written in the selected memory cell; a sense amplifier SA for amplifying a data signal read from the selected memory cell; and a data output circuit DO for externally outputting the data signal amplified by the sense amplifier SA as a read data signal Dout. Further, DRAM chip 1 includes a control signal generating circuit CG for generating, based on external control signals such as a low-active row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE, internal control signals for controlling these functional portions. In the following description, low-active signals are represented with / attached to the reference characters.
In the memory cell array MCA, memory cells arranged in the same row are all connected to the same word line (not shown), and the memory cells arranged in the same column are all connected to the same bit line (not shown).
Address buffer AB externally receives n+1 bits of address signals. The respective bits of signals A0, A1, . . . , An constituting the address signal are applied in parallel to address buffer AB. Address buffer AB buffers these signals A0 to An and apply these signals to row decoder RD and column decoder CD. Row decoder RD decodes the address signal from address buffer AB and selects any of the rows of memory cells included in memory cell array MCA, and activates the word line connected to the selected row of the memory cells. Column decoder CD decodes the address signal from address buffer AB and selects any of the columns of memory cells included in memory cell array MCA, as well as the bit line and the sense amplifier SA connected thereto.
In data writing, a data signal Din is externally applied to data input circuit DI. Data input circuit DI applies the data signal Din only to the sense amplifier SA and the bit line which are connected to the column of memory cells selected by column decoder CD. Therefore, the external data is written only in the memory cell which is connected to this bit line and to the word line activated by row decoder RD.
In data reading, only the data stored in memory cells connected to the word line which has been activated by row decoder RD appear as electric signals on corresponding bit lines, and amplified by the sense amplifier SA. Out of the amplified stored data signals, only that signal appearing on the bit line which is connected to the column of memory cells selected by column decoder CD is applied to data output circuit DO. Data output circuit DO outputs externally the data signal from sense amplifier SA as a read data signal Dout.
Since DRAM chip 1 includes the above described internal circuitry, it includes, as external terminals, a plurality of bonding pads for receiving externally the control signals such as row address strobe signal, column address strobe signal and write enable signal; n+1 bonding pads for receiving externally the n+1 bits of address signals; a bonding pad for externally receiving the data to be written to the memory cell array MCA; a bonding pad for receiving data read from memory cell array MCA through data output circuit DO; and two bonding pads for receiving externally the voltage for operating the internal circuitry. One of the aforementioned two bonding pads receives general ground potential Vss, and the other receives the general power supply potential Vcc.
FIG. 12 shows an actual arrangement of the bonding pads and main internal circuitry on a DRAM chip such as described above. Referring to FIG. 12, the DRAM chip 1 includes two memory cell arrays 2 having two sub arrays divided in the direction of rows. More specifically, one of these two memory cell arrays is divided into sub arrays MCA1 and MCA2, while the other one is divided into sub arrays MCA3 and MCA4. Sense amplifiers SA1 and SA2 are provided corresponding to sub arrays MCA1 and MCA2, respectively. Similarly, sense amplifiers SA3 and SA4 are provided corresponding to sub arrays MCA3 and MCA4, respectively. A column decoder CD1 and a row decoder RD1 are both provided common to sub arrays MCA1 and MCA2. Similarly, a column decoder CD2 and a row decoder RD2 are both provided common to sub arrays MCA3 and MCA4. On chip 1, the memory cell array divided into sub arrays MCA1 and MCA2 and a circuitry portion provided correspondingly, and the memory cell array divided into sub arrays MCA3 and MCA4 and a circuitry portion provided correspondingly are arranged on the right and left sides, respectively, as different blocks. An address buffer AB is arranged at the center of chip 1. Bonding pads 2 are arranged along the longitudinal direction near the outer side of chip 1. Each of the bonding pads 2 is connected to any of the functional portion constituting the internal circuitry by means of an interconnection layer formed on chip 1, corresponding to the signal which the bonding pad receives. For example, a bonding pad receiving an address signal is connected to address buffer AB.
Address buffer AB receiving n+1 bits of address signals generally includes a buffer AB0 for buffering the least significant bit signal A0, a buffer AB1 for buffering the second least significant bit signal A1, . . . , and a buffer ABn for buffering the most significant bit signal An. On chip 1, a bonding pad receiving signal A0, a bonding pad receiving signal A1, . . . , a bonding pad receiving signal An are connected to buffers AB0, AB1, . . . , ABn, respectively by means of separate interconnection layers. FIG. 12 shows, as a representative, interconnection layer 20 which connects a buffer ABi with a bonding pad 200 receiving a signal Ai (i=0, 1, 2, . . . , n) out of the n+1 signals constituting the address signal.
Recently, the internal circuitry of a semiconductor device realizing complicated functions such as a DRAM has come to be formed of larger number of elements. Since the degree of integration of the semiconductor device is increased, the size of the chip of the semiconductor device is also increased. The larger the chip size becomes, the longer the interconnection layer becomes for connecting the bonding pad with the internal elements. Therefore, a capacitance (stray capacitance) generated between the interconnection layer and the semiconductor substrate on which the interconnection layer is formed becomes larger. For this reason, driving capability of a circuit externally supplying signals to the bonding pad must be improved. In a semiconductor memory, for example, as the number of memory cells included in the memory cell array increases, the number of bits of the address signals is increased. Therefore, the number of bonding pads to be provided on the semiconductor memory chip to receive the address signals is also increased. Consequently, some of the bonding pads receiving the address signals are provided apart from the internal circuitry to which these pads are to be connected. In a DRAM, for example, bonding pad 200 receiving one address signal Ai is provided near the end portion in the longitudinal direction of chip 1, that is, considerably apart from buffer ABi to which the pad is to be connected. Therefore, the length of interconnection layer 20 connecting bonding pad 200 and buffer ABi is about one half of the longer side of chip 1. The length of the longer side of a 4M bit DRAM chip is about 14 mm, for example, and therefore the length of interconnection layer 20 in that case is about 7 mm. In this example, the interconnection layer 20 has a stray capacitance of about 1.2 pF. Each of the bonding pads 2 is connected to an external pin constituting a lead frame (not shown). A total capacitance of each of the external pins (hereinafter referred to as address signal pins) connected to the bonding pads receiving the address signals, the bonding pads connected thereto and of the metal wires connecting the address signal pins and the bonding pads, is, in general, about 3.5 pF. Namely, the capacitance existing between the external circuitry (not shown) generating the address signal Ai and buffer ABi is about 4.7 pF (=3.5 pF+1.2 pF). More specifically, the aforementioned external circuitry must have at least a driving capability enough to quickly charge/discharge a capacitor having the capacitance of 4.7 pF.
In actual practice, a plurality of such semiconductor memories are used combined to realize writing and reading of a large amount of information. In such a case, the plurality of semiconductor memories are mounted on one memory board formed of an insulating material, and address signals are supplied from a common external circuitry. When 100 4M bit DRAMs are mounted on one memory board, the external circuitry generating an address signal Ai must have a driving capability enough to quickly charge the total capacitance of 350 pF (3.5 pF.times.100) of a total of 100 address signal pins provided corresponding to the address signal Ai out of external pins of 100 DRAM chips, 100 metal wires respectively connected to 100 address signal pins and 100 bonding pads 200, as well as the total capacitance of 120 pF (=1.2 pF.times.100) of 100 interconnection layers 20 connecting these 100 bonding pads 200 to the buffers ABi of the corresponding chips.
In order to solve such a problem, the stray capacitance of the interconnection layer connecting the bonding pad with the internal circuitry must be made smaller. In a DRAM, for example, the driving capability of the external circuitry generating signals which are to be externally supplied to external pins is enough to quickly charge/discharge the capacitance of about 5 pF or less conventionally. Therefore, in order to avoid the increase of the driving capability required for the external circuitry providing signals to the DRAM accompanying the increase of storage capacity of the DRAM, the total capacitance posed between the respective external pins of the DRAM and the internal circuitry connected thereto (including the capacitance of the external pins themselves) must be about 5 pF or less even in a DRAM having large storage capacity. Further, the aforementioned total capacitance should preferably be 4 pF or less in consideration of variation during manufacturing of the lead frames. Therefore, the stray capacitance of the interconnection layer connecting an address buffer and a bonding pad receiving the address signal out of the bonding pads of the DRAM must be 0.5 pF (=4 pF-3.5 pF) or less, regardless of the storage capacity of the DRAM. However, in case of a 4M bit DRAM, the stray capacitance of the interconnection layer 20 connecting the buffer ABi with a bonding pad 200 shown in FIG. 12 is as large as about 1.2 pF, as described above.
Japanese Utility Model Laying Open No. 63-40896 shows a method of decreasing stray capacitance of the interconnection layer connecting the bonding pad to the internal circuitry. According to this Utility Model Laying Open 63-40896, an amplifying circuit is newly provided between the bonding pad and the internal circuitry to be connected to the pad. On a semiconductor substrate, the amplifying circuit is provided very close to the bonding pad, and the amplifying circuit amplifies the signal externally applied to the bonding pad, and applies the amplified signal to the internal circuitry. FIG. 13 shows electrical path between the bonding pad and the internal circuitry to be connected thereto in the semiconductor device disclosed in Japanese Utility Model Laying-Open No. 63-40896. FIG. 13 shows each of the interconnection layers connecting internal circuits in the form of an equivalent circuitry including resistance elements having resistance values corresponding to the length thereof, and capacitances (stray capacitances) generated between the interconnection layers and the semiconductor chip substrate.
Referring to FIG. 13, amplifying circuits 23 and 24 are newly provided corresponding to bonding pads 21 and 22 receiving address signals Aj1 and Aj2, respectively. Amplifying circuit 23 is provided near bonding pad 21, and amplifying circuit 24 is provided near bonding pad 22. Further, a switch 27 is newly provided at a succeeding stage of amplifying circuits 23 and 24. An output signal of switch 27 is applied to address buffer 29. Output signals from amplifying circuits 23 and 24 are applied to switch 27. Switch 27 switches and outputs the output signal from amplifying circuit 23 or the output signal from amplifying circuit 24. Therefore, address signal Aj1 or address signal Aj2 is switched and applied to address buffer 29. Consequently, two signals Aj1 and Aj2 constituting the address signals are respectively buffered and a complementary signal pair a,/a by means of a single buffer 29.
Bonding pad 21 and amplifying circuit 23, bonding pad 22 and amplifying circuit 24, amplifying circuit 23 and switch 27, amplifying circuit 24 and switch 27, and switch 27 and address buffer 29 are connected to each other by interconnection layers formed on semiconductor chip 1. However, since amplifiers 23 and 24 are provided close to bonding pads 21 and 22, respectively, interconnection layer 30 connecting bonding pad 21 and amplifying circuit 23 and interconnection layer 31 connecting bonding pad 22 and amplifying circuit 24 are very short. Therefore, stray capacitances of interconnection layers 30 and 31 are so small that they can be neglected. If bonding pads 21 and 22 are positioned very much apart from address buffer 29, interconnection layer 25 connecting amplifying circuit 23 and switch 27, interconnection layer 26 connecting amplifying circuit 24 and switch 27, and interconnection layer 28 connecting switch 27 and address buffer 29 are long. Therefore, stray capacitances and resistances of these interconnection layers 25, 26 and 28 are considerably larger than the stray capacitances and resistances of interconnection layers 30 and 31. However, the interconnection layers 25, 26 and 28 are driven by amplifying circuits 23 and 24. Therefore, attenuation of signals in the interconnection layer 25 because of larger stray capacitance of the interconnection layer 25, attenuation of signals in the interconnection layer 26 because of larger stray capacitance of interconnection layer 26 and attenuation of signals in interconnection layer 28 because of larger stray capacitance of interconnection layer 28 are no problem. More specifically, the driving capability of the external circuitry generating address signals Aj1 and Aj2 may be set corresponding to the stray capacitances of interconnection layers 30 and 31. Even if the driving capability of the external circuit is not very much improved, speed and accuracy signal transmission to internal circuitry is assured.
FIG. 14 shows a circuitry disclosed in Japanese Utility Model Laying Open No. 63-40896 as a specific example of the amplifying circuits 23 and 24 shown in FIG. 13. Referring to FIG. 14, each of the amplifying circuits 23 and 24 includes, for example, inverters INV1, INV2 and INV3 connected in series.
Inverter INV1 includes a P channel MOS transistor Q2 and an N channel MOS transistor Q3 receiving at their gates an address signal Aj from a corresponding bonding pad and a P channel MOS transistor Q1 having its gate grounded. Transistors Q1, Q2 and Q3 are connected in series between a power supply Vcc and the ground GND. Since transistor Q1 is always conductive, transistors Q2 and Q3 serve as an inverter for inverting address signal Aj. More specifically, if the potential of address signal Aj is lower than the threshold voltage of transistor Q2 and the threshold voltage of transistor Q3, only the transistor Q2 is rendered conductive, whereby the potential of the power supply Vcc is applied to the node between transistors Q2 and Q3. Conversely, if the potential of address signal Aj is higher than the threshold voltage of transistor Q2 and than the threshold voltage of transistor Q3, only the transistor Q3 is rendered conductive, whereby the potentials of transistors Q2 and Q3 are lowered to the ground potential. The threshold voltage of transistor Q2 is set to be higher than the potential of the address signal Aj corresponding to the logic value of " 0", and the threshold voltage of transistor Q3 is set to be lower than the potential of address signal Aj corresponding to the logic value of "1". Therefore, the node between transistors Q2 and Q3 is supplied with a current from power supply Vcc in response to the address signal Aj having the logic value 0, and the current at this node is drawn to the ground GND in response to the address signal Aj having the logic value 1. Consequently, the amplitude of the output potential from inverter INV1 is about the output voltage of external power supply. Inverter INV2 includes a P channel MOS transistor Q4 and an N channel MOS transistor Q5 connected in series between power supply Vcc and the ground GND. Similarly, inverter INV3 includes a P channel MOS transistor Q6 and an N channel MOS transistor Q7 connected in series between the power supply Vcc and the ground GND. An output potential from inverter INV1 is applied to the gates of transistors Q4 and Q5, and an output potential from inverter INV2 is applied to the gates of transistors Q6 and Q7. Therefore, at the node between transistors Q4 and Q5, a logic level inverse to the output logic level from inverter INV1 appears, and at the node between transistors Q6 and Q7, a potential having the inverse logic level to the output logic level of inverter INV2 appears. Therefore, the address signal Aj with its logic level inverted is output from the amplifying circuit.
Differential voltage (hereinafter referred to as amplitude of address signal Aj) between the potential of the address signal Aj having the logic value of 0 and the potential of the address signal Aj having the logic value of 1 is smaller than the output voltage of the aforementioned external power supply, the amplitude of the address signal after inversion by inverter INV1 is larger than the address signal Aj before inversion; the amplitude of the address signal further inverted by inverter by INV2 is larger than the address signal before inversion by inverter INV2; and the amplitude of the address signal further inverted by inverter INV3 is larger than that of the address signal before inversion by inverter INV3. Namely, the address signal Aj has its logic level successively inverted by inverters INV1, INV2 and INV3, and its amplitude widened to about the output voltage of the aforementioned external power supply by means of these three inverters. Consequently, the output signal Ajr from the amplifying circuit is an amplified signal of the original address signal Aj.
As described above, in one conventional method of reducing driving capability of the external circuitry supplying signals to the bonding pads by reducing stray capacitances of interconnection layers connecting the bonding pads with internal circuitry in a semiconductor device, an amplifying circuit electrically connected to a bonding pad and to the internal circuitry to which the bonding pad is to be connected inherently is provided near the bonding pad. However, the amplifying circuit is adapted to operate only in response to the signal externally applied to the corresponding bonding pad. Consequently, the following problem arises.
Referring to FIG. 14, to the amplifying circuit, only the address signal Aj externally applied to the corresponding bonding pad is input. Therefore, the potential of the output signal Ajr of the amplifying circuit is determined by the states of transistors Q2 and Q3 (that is, dependent on whether they are on or off). Assume that the amplifying circuit shown in FIG. 14 is applied to a DRAM chip.
FIGS. 15(a)-15(c) are timing charts showing timings of switching external control signals and the address signal in the DRAM. Referring to FIGS. 14 and 15(a)-15(c), in the DRAM, the row address strobe signal /RAS (FIG. 5 (a)) falls to the low level at time t2 earlier than time t3 at which the column address strobe signal /CAS falls to the low level corresponding to the logic value of 0 during data writing and data reading. Thereafter, the row address strobe signal /RAS rises to the high level corresponding to the logic value 1 at time t5, at the same timing as the column address strobe signal /CAS. Data writing and data reading are carried out during the period in which the row address strobe signal /RAS is at the low level. More specifically, in data writing, the row decoder RD, column decoder CD and the data input circuit DI are enabled only during the period in which the row address strobe signal RAS is at the low level. In data reading, the row /decoder RD, the column decoder CD and data output circuit DO are enabled during the period in which the row address strobe signal /RAS is at the low level (see FIG. 11). The row decoder RD is enabled in response to the fall of the row address strobe signal RAS to the low level, while the column decoder CD is enabled in response to the fall of the column address strobe signal /CAS to the low level. Therefore, in the period when the row address strobe signal /RAS is at the low level, the row address signal and the column address signal corresponding to the memory cell to which or from which data is to be written or read must be surely applied to the row decoder RD and the column decoder CD while the row address strobe signal /RAS is at the low level. For this purpose, the row address signal, that is, the signal indicating the column in which the memory cell to which or from which data is to be written or read is arranged, and the column address signal, that is, the signal indicating the column in which the memory cell to which or from which data is to be written or data is to be read is positioned, must be externally applied little earlier than the enablement of the row decoder RD and the column decoder CD. Generally, the row address signal and the column address signal are applied to the same bonding pad.
Accordingly, as shown in FIG. 15 (c), in the DRAM, the row address signal R1 and the column address signal C1 indicating the position of said memory cell are applied at time t1 earlier than the time t2 of the fall of the row address strobe signal /RAS and at a time earlier than the time t3 of the fall of the column address strobe signal /CAS, respectively. As the row address signal R1 and the column address signal C1 are successively applied in the period when the row address strobe signal /RAS is at the low level, data is written to or data is read from the memory cell corresponding to the crossing of the row indicated by the row address signal R1 and the column indicated by the column address signal C1. The row address signal R1 and the column address signal C1 are both latched in the corresponding internal circuit, therefore they should be kept supplied externally for a time period necessary for them to be latched in the corresponding internal circuitry. Therefore, after the time t4 by which time the row address signal R1 and the column address signal C1 have been latched in the corresponding internal circuitry, signal potentials of any bits corresponding to the address signals may have arbitrary values. Therefore, from time t4 to the time t6 little earlier than the time t7 at which the row address strobe signal /RAS falls next, the potential of the bonding pads receiving the address signals may have any value, or it may be unstable. In the following, the period in which the row address strobe signal /RAS is at the low level is called an operational period of the DRAM, while the period in which the row address strobe signal is at the high level is called a standby period of the DRAM.
In any operational period, the column address strobe signal /CAS falls after the fall of the row address strobe signal /RAS. Therefore, at the start of the next operational period (time t7 to t10) following the first operational period (time t1 to time t5) of FIGS. 15(a)-15(c), the row address signal R2 and the column address signal C2 are applied in this order, indicating the position of an arbitrary memory cell. More specifically, the row address signal R2 is applied from time t6 little earlier than the time t7 at which the row address strobe signal /RAS falls, and the column address signal C2 is applied a little earlier than t8 at which the column address strobe signal /CAS falls. After the time t9 by which time the row address signal R2 and the column address signal C2 have been already latched in the corresponding internal circuitry, the potentials of any bonding pads receiving the address signals may have any values.
Generally, an input signal to the DRAM is applied with the TTL level. In other words, the potential not lower than 2.4 V is input as a signal having the logic value of "1" and a potential not higher than 0.8 V is input as a signal having the logic value of "0", to the internal circuitry of the DRAM. Since the DRAM is a MOS-IC formed of MOS transistors, the internal circuitry of the DRAM recognizes the power supply potential and the ground potential 0 V as signals having the logic values of 1 and 0, respectively. Generally, the power supply potential of a MOS-IC such as a DRAM is 5 V. Therefore, the threshold voltage of the inverter in the DRAM is set at about 2.5 V, that is, middle of the power supply potential 5 V and the ground potential 0 V. Referring to FIG. 14, transistors Q2, Q4 and Q6 are designed such that they are completely turned off when the gate potential rises to about 5 V, and that they are completely turned on when the gate potential lowers to about 0 V. Conversely, transistors Q3, Q5 and Q7 are designed such that they are completely turned on when the gate potential rises to about 5 V, and they are completely turned off when the gate potential lowers to about 0 V. If the gate potential is near 2.5 V, the transistors Q1 to Q7 are at the state corresponding to the boundary between the on and off states. More specifically, the conduction resistance of each of the transistors Q1, Q2, Q4 and Q6 gradually becomes smaller as the gate potential thereof lowers from the middle potential between the power supply potential and the ground potential, while conduction resistance of each of the transistors Q3, Q5 and Q7 gradually lowers as the gate potential thereof increases from the middle potential between the power supply potential and the ground potential.
Therefore, each of the inverters INV1, INV2 and INV3 outputs a potential lower than the intermediate potential when the input potential is higher than the intermediate potential between power supply potential and the ground potential, and it outputs a potential higher than the intermediate potential when the input potential is lower than the intermediate potential. Therefore, if the potential of the address signal Aj is at a potential corresponding to the logic value 1 of the TTL level (=2.4 V), not only transistor Q1 but also transistors Q2 and Q3 are turned ON, in inverter INV1. Thus, a through current flows from power supply Vcc to the ground GND through transistors Q1, Q2, and Q3. Consequently, potential at the node between transistors Q2 and Q3 is determined dependent on the ratio of conduction resistances of the transistors Q1 and Q2 and conduction resistance of transistor Q3, and hence it becomes lower than the intermediate potential between the power supply potential and the ground potential. Accordingly, the output potential from inverter INV2 becomes higher than the intermediate potential between the power supply potential and the ground potential, and thus the output potential from inverter INV3 becomes lower than the intermediate potential. Namely, a logic value inverse to the logic value represented by the address signal Aj is output from inverter INV3. Conversely, if the address signal Aj is at a potential corresponding to logic value 0 at the TTL level (=0.8 V), transistors Q2 and Q3 are respectively set to approximately complete ON and complete OFF as compared with the case when the address signal Aj is at a potential corresponding to the logic value 1 of the TTL level, the output potential of inverter INV1 attains about the supply potential 5 V. Thus the output potential from inverter INV2 becomes the ground potential, and the output potential of inverter INV3 becomes the power supply potential. Namely, in this case also, a logic value which is inverse to the logic value represented by the address signal Aj is output from inverter INV3.
In this manner the amplifying circuit shown in FIG. 14 inverts and amplifies the input external signal having the TTL level to the MOS level and outputs the same. However, in the period from time t4 to t6 in FIG. 15, that is, the period in which the potential of the address signal Aj may have any value, there is a problem that a through current continuously flows in inverter INV1. More specifically, in such a period, generally, the potential of each bit constituting the address signal is fixed to a potential corresponding to the logic value 1 or 0 of the TLL level, and therefore transistors Q1 and Q2 in inverter INV1 are not completely turned off. Especially when any of the n+1 signal potentials constituting the address signal is fixed at a potential corresponding to the logic value 1 of the TTL level, conduction resistances of transistors Q1 and Q2 both become sufficiently small in inverter INV1 in the first stage of the amplifying circuit provided corresponding to that signal. Consequently, a through current of considerable magnitude continuously flows during the standby period in the inverter INV1. This leads to larger power consumption of the DRAM.